[REF] How to checkpoint FPGA state?

rs,

I am only familiar with our ISE Impact JTAG cable, and the software we provide.

http://www.xilinx.com/products/design_tools/logic_design/design_entry/impact.htm
Thru the Impact software, one can program the device, read the system monitor to determine the temperature, and the voltages, and perform a verify.
The verify step places the readback contents of the device into a file called impact.bin if the proper environment variables are set by the user (in Windows XP, these are

set XIL_IMPACT_VIRTEX_DUMPBIN=1
set XIL_IMPACT_IGNORE_MASK_FILE=1

Parsing the readback file can be a bit arduous, as it is in binary format (I use a binary file editor that expresses the file in hex and binary), and we do not supply a map.  However, the .msk file (mask file) supplies information about where capture, and restore bits, and other dynamic content is located (so it may be ignored, as it changes).  Along with the ‘diff’ command (comapre two files, and express the differences, it isn’t too hard to find initial conditions (by changing them in your design), and other bit locations of interest.

Sorry I can not be of more help,

Austin Lesea
Principal Engineer
Xilinx San Jose
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